In steps one and two, you will build an S-R latch and then a D latch from your S-R latch, before building D flip-flop. Since you need two D latches (and therefore two S-R latches) to build a D flip-flop, I recommend the following layout strategy.
Build an S–R latch on yor protoboard using the following circuit diagram:
Test your S–R latch. How do you know it is storing a value?
Add the necessary gates to turn your S–R latch into a D latch. Recall that a D latch has two inputs and two outputs:
Test your D latch to verify that it stores the correct value, and only updates the stored value when the clock input is high.
Connect the $C$ input of your D latch to the clock signal on the left side of your protoboard. You should hook a logic indicator light up to the clock input so you can monitor it. Set your clock on the
TTL option, square wave, and a low frequency (Hz, not KHz, and 1, not 10 or 100).
With the clock set slow enough, you should be able to watch the value on $D$ update the latch state only when the clock is high.
What happens when you change $D$ while $C$ is still high?
Build a second D latch and connect it to your first D latch to build an edge-triggered flip-flop. The following figure shows a D flip-flop that stores an input value on the clock’s falling edge.
Once you have completed this step, please have the instructor or a mentor sign off on your circuit.
For the final step of this lab, you may choose one of the two exercises. You must complete at least one, but you do not need to complete both to earn full credit on the lab.
Once you have completed one of the options, please have the instructor or a mentor sign off on your circuit.
Using a flip-flop, you can cut the frequency of a clock signal in half. Design a circuit to do this, then implement it using the flip-flop you built in step 4. If you have trouble coming up with your design, I can share a hint.
Drive the input with the protoboard’s clock input, and use logic indicators to verify that the input clock cycles twice as fast as the output clock.
Caution: There is a limit to how fast you can cycle a clock input to TTL chips and still observe the expected behavior. If you set the clock frequency too high, your flip-flop may not “settle” in its final state before the clock input changes.
Using the two D latches you built for your flip-flop, implement a simple 2x1 register file (two registers, each of one bit). Your circuit should have the following inputs and outputs:
This circuit will require a simple decoder and multiplexor. The one bit versions of these components can be built with very few gates, so try to think up a simple implementation before building your circuit.
This lab is adapted from a lab introduced to Grinnell College by Marge Coahran and updated by Janet Davis.
The circuit diagrams are Figures B.8.1 (p. B-50), B.8.2 (p B-52), and B.8.4 (p. B-53) from
Patterson D. A. & Hennessy J. L. (2014). Computer organization and design: The hardware/software interface (5th ed.). Waltham, MA: Morgan Kaufmann.